This structure describes the PCI configuration space for PCI devices. All PCI devices have a common set of registers that include VendorID, DeviceID, and so on. This structure differs for PCI devices of header type 0 for devices, of header type 1 for PCI-PCI bridges, and of header type 2 for PCI-CardBus bridges. For more information, see the PCI Local Bus Specification, revision 2.1 or 2.2.
typedef struct _PCI_COMMON_CONFIG {
USHORT VendorID;
USHORT DeviceID;
USHORT Command;
USHORT Status;
UCHAR RevisionID;
UCHAR ProgIf;
UCHAR SubClass;
UCHAR BaseClass;
UCHAR CacheLineSize;
UCHAR LatencyTimer;
UCHAR HeaderType;
UCHAR BIST;
union {
struct _PCI_HEADER_TYPE_0 {
ULONG BaseAddresses[PCI_TYPE0_ADDRESSES];
ULONG CIS;
USHORT SubVendorID;
USHORT SubSystemID;
ULONG ROMBaseAddress;
ULONG Reserved2[2];
UCHAR InterruptLine;
UCHAR InterruptPin;
UCHAR MinimumGrant;
UCHAR MaximumLatency;
} type0;
struct _PCI_HEADER_TYPE_1 {
ULONG BaseAddresses[PCI_TYPE1_ADDRESSES];
UCHAR PrimaryBusNumber;
UCHAR SecondaryBusNumber;
UCHAR SubordinateBusNumber;
UCHAR SecondaryLatencyTimer;
UCHAR IOBase;
UCHAR IOLimit;
USHORT SecondaryStatus;
USHORT MemoryBase;
USHORT MemoryLimit;
USHORT PrefetchableMemoryBase;
USHORT PrefetchableMemoryLimit;
ULONG PrefetchableMemoryBaseUpper32;
ULONG PrefetchableMemoryLimitUpper32;
USHORT IOBaseUpper;
USHORT IOLimitUpper;
ULONG Reserved2;
ULONG ExpansionROMBase;
UCHAR InterruptLine;
UCHAR InterruptPin;
USHORT BridgeControl;
} type1;
struct _PCI_HEADER_TYPE_2 {
ULONG BaseAddress;
UCHAR CapabilitiesPtr;
UCHAR Reserved2;
USHORT SecondaryStatus;
UCHAR PrimaryBusNumber;
UCHAR CardbusBusNumber;
UCHAR SubordinateBusNumber;
UCHAR CardbusLatencyTimer;
ULONG MemoryBase0;
ULONG MemoryLimit0;
ULONG MemoryBase1;
ULONG MemoryLimit1;
USHORT IOBase0_LO;
USHORT IOBase0_HI;
USHORT IOLimit0_LO;
USHORT IOLimit0_HI;
USHORT IOBase1_LO;
USHORT IOBase1_HI;
USHORT IOLimit1_LO;
USHORT IOLimit1_HI;
UCHAR InterruptLine;
UCHAR InterruptPin;
USHORT BridgeControl;
USHORT SubVendorID;
USHORT SubSystemID;
ULONG LegacyBaseAddress;
UCHAR Reserved3[56];
ULONG SystemControl;
UCHAR MultiMediaControl;
UCHAR GeneralStatus;
UCHAR Reserved4[2];
UCHAR GPIO0Control;
UCHAR GPIO1Control;
UCHAR GPIO2Control;
UCHAR GPIO3Control;
ULONG IRQMuxRouting;
UCHAR RetryStatus;
UCHAR CardControl;
UCHAR DeviceControl;
UCHAR Diagnostic;
} type2;
} u;
UCHAR DeviceSpecific[108];
} PCI_COMMON_CONFIG , *PPCI_COMMON_CONFIG;
Members
VendorID
| PCI vendor identifier register.
|
DeviceID
| PCI device identifier register.
|
Command
Status
RevisionID
| PCI revision identifier register.
|
ProgIf
| PCI programming interface register.
|
SubClass
| PCI device sub-class register.
|
BaseClass
| PCI device base-class register.
|
CacheLineSize
| PCI cache line size register.
|
LatencyTimer
| PCI latency timer register.
|
HeaderType
| PCI header type register. 0 indicates a normal PCI device, 1 indicates a PCI-PCI bridge, and 2 indicates a PCI-CardBus bridge.
|
BIST
| PCI built-in self test register.
|
BaseAddresses
| Array of PCI base address registers. Normal PCI devices have 6 base address registers, while PCI-PCI bridges have 2 and PCI-CardBus bridges have 1.
|
CIS
| CardBus CIS pointer register.
|
SubVendorID
| PCI subsystem vendor identifier register.
|
SubSystemID
| PCI subsystem identifier register.
|
ROMBaseAddress
| PCI ROM base address register.
|
Reserved2, Reserved3, Reserved4
InterruptLine
| PCI interrupt line register.
|
InterruptPin
| PCI interrupt pin register.
|
MinimumGrant
| PCI minimum grant register.
|
MaximumLatency
| PCI maximum latency register.
|
BaseAddress
| PCI base address register.
|
PrimaryBusNumber
| PCI primary bus number register.
|
SecondaryBusNumber
| PCI secondary bus number register.
|
SubordinateBusNumber
| PCI subordinate bus number.
|
SecondaryLatencyTimer
| PCI secondary latency timer.
|
IOBase
| Lower 8 bits of PCI I/O base address register.
|
IOLimit
| Lower 8 bits of PCI I/O limit address register.
|
SecondaryStatus
| PCI secondary status register.
|
MemoryBase
| PCI memory base address register.
|
MemoryLimit
| PCI memory limit address register
|
PrefetchableMemoryBase
| Lower 16 bits of PCI prefetchable memory base address register.
|
PrefetchableMemoryLimit
| Lower 16 bits of PCI prefetchable memory limit address register.
|
PrefetchableMemoryBaseUpper32
| Upper 32 bits of PCI prefetchable memory base address register.
|
PrefetchableMemoryLimitUpper32
| Upper 32 bits of PCI prefetchable memory limit address register.
|
IOBaseUpper
| Upper 16 bits of PCI I/O base address register.
|
IOLimitUpper
| Upper 16 bits of PCI I/O limit address register.
|
ExpansionROMBase
| PCI expansion ROM base address register.
|
BridgeControl
| PCI bridge control register.
|
CapabilitiesPtr
| PCI capabilities pointer register.
|
SecondaryStatus
| PCI secondary status register.
|
CardbusBusNumber
| CardBus bus number register.
|
CardbusLatencyTimer
| CardBus latency timer register.
|
MemoryBase0
| CardBus memory base address register 0.
|
MemoryLimit0
| CardBus memory limit address register 0.
|
MemoryBase1
| CardBus memory base address register 1.
|
MemoryLimit1
| CardBus memory limit address register 1.
|
IOBase0_LO
| Lower 16 bits of CardBus I/O base address register 0.
|
IOBase0_HI
| Upper 16 bits of CardBus I/O base address register 0.
|
IOLimit0_LO
| Lower 16 bits of CardBus I/O limit address register 0.
|
IOLimit0_HI
| Upper 16 bits of CardBus I/O limit address register 0.
|
IOBase1_LO
| Lower 16 bits of CardBus I/O base address register 1.
|
IOBase1_HI
| Upper 16 bits of CardBus I/O base address register 1.
|
IOLimit1_LO
| Lower 16 bits of CardBus I/O limit address register 1.
|
IOLimit1_HI
| Upper 16 bits of CardBus I/O limit address register 1.
|
LegacyBaseAddress
| CardBus legacy base address register.
|
SystemControl
| CardBus system control register.
|
MultiMediaControl
| CardBus multimedia control register.
|
GeneralStatus
| CardBus general status register.
|
GPIO0Control, GPIO1Control, GPIO2Control, GPIO3Control
| CardBus GPIO control registers
|
IRQMuxRouting
| CardBus IRQ multiplexer routing register.
|
RetryStatus
| CardBus retry status register.
|
CardControl
| CardBus card control register.
|
DeviceControl
| CardBus device control register.
|
Diagnostic
| CardBus diagnostic register.
|
DeviceSpecific
| Device specific registers in the PCI configuration space, varies by device.
|
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